Direct bonding of GaN and SiC; a novel technique for electronic device fabrication

Contributors:   Jaeseob Lee, Robert F. Davis and Robert J. Nemanich

ABSTRACT

The direct bonding method is applied to the GaN/SiC system, and the processing conditions for successful direct bonding are clarified. Direct bonding of GaN/SiC is achieved at 900°C. The direct bonding of GaN to Si-face SiC is very dependent on the choice of chemical treatments but the bonding of GaN to C-face SiC is less dependent on surface preparation. It is found that an oxide-cleaned surface is essential to achieve good reproducibility of bonding. The electrical properties of the bonded interfaces are also characterized. If a native oxide is present when the bonded interface is prepared, the current through the interface is decreased, which is attributed to an energy barrier due to the presence of charged interface states. Cross section transmission electron microscopy indicates 10nm spaced dislocations at the interface, which form to accommodate the lattice mismatch and twist misfit. In some regions an amorphous oxide layer forms at the interface, which is attributed to inadequate surface preparation prior to bonding. Directly bonded GaN/SiC heterojunction diodes have been fabricated and characterized. The Ga-face (0001) n-type 2H GaN films were directly bonded to the Si-face or C-face (0001, 000-1) p-type 6H SiC. The I-V characteristics display diode ideality factors, saturation currents and energy barrier heights of 1.5±0.1, 10-13A/cm2, 0.75±0.10 eV for the Ga/Si interface and 1.2±0.1, 10-16A/cm2, 0.56±0.10 eV for the Ga/C interface. The built-in potential was determined from capacitance-voltage measurements to be 2.11±0.10 eV and 2.52±0.10 eV for the Ga/Si interface and the Ga/C interface, respectively. From the built-in potential the energy band offsets are determined to be ΔEC=0.87±0.10 eV and ΔEV=1.24±0.10 eV for the Ga/Si interface and ΔEC=0.46±0.10 eV and ΔEV=0.83±0.10 eV for the Ga/C interface.

Publisher: International Journal of High Speed Electronics and Systems,   Volume: 14,   83-105 ||  Published: 2004-01 ||   Read more...