Materials and processes for high k gate stacks: Results from the FEP transition center
Contributors: Carl Osburn, Steve Campbell, Alex Demkov, Eric Eisenbraun, Eric Garfunkel, Torgny Gustafsson, Angus I. Kingston, Jack Lee, dan Lichtenwalner, Gerry Lucovsky, T.P. Ma, Jon-Paul Maria, Veena Misra, Robert J. Nemanich, Greg Parsons, Darrell Schlom, Susanne Stemmer, Robert M. Wallace, and Jerry Whitten
ABSTRACT
A wide variety of materials and processes for high k dielectrics and metal gate electrodes have been studied as replacements for poly-Si/SiO2 or SiON in advanced CMOS devices. Care must be taken with the interfacial layer to control not only the nitrogen content but its spatial location. Nanocrystallization of the high k dielectric and the corresponding formation of charge and trapping levels associated with defects in the dielectric present one of the current challenges. Control of the workfunction of the gate electrode is shown to depend on many variables, including oxygen content and the material used for the capping layer on the metal gate. The hafnium oxide family of materials, along with metal alloy gates, is seen to provide the best solution for equivalent oxide thicknesses (EOT's) < 0.7 nm, but higher k dielectrics and thinner interfacial layers are needed below 0.7 nm.