High-K dielectrics on Si
With conventional thermal oxides and oxynitrides approaching the limit of their effectiveness as gate dielectrics, the exploration of alternative materials is becoming increasingly important.
Improving performance in field effect transistors (FETs) requires that the sheet charge density in the channel be increased. Increasing the sheet charge density, in turn, requires that gate capacitance be increased. Typically this is achieved by reducing the thickness of the gate dielectric however, as the gate dielectric thickness is reduced below 2nm, direct tunneling between the gate and channel becomes significant, leading to increased power consumption.
One solution is to employ a high-K material, allowing increased capacitance with physically thicker layers, thereby giving both reduced tunneling current and the desired increase in performance. The fundamental criteria for a gate dielectric include band offsets that will block both electrons and holes, chemical stability in contact with the silicon substrate and the gate material, and a low density of interface electronic states.